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1 fn6031.4 isl84521, isl84522, isl84523 low-voltage, single and dual supply, quad spst, analog switches the intersil isl84521, isl84523, isl84523 devices are cmos, precision, quad analog s witches designed to operate from a single +2v to +12v supply or from a ? 2v to ? 6v supply. targeted applications include battery powered equipment that benefit from the devices low power consumption (<1 ? w), low leakage currents (1na max) , and fast switching speeds (t on = 45ns, t off = 15ns). a12 ? maximum r on flatness ensures signal fidelity, while channel-to-channel mismatch is guaranteed to be less than 4 ? . the isl84521, isl84522, isl84523 are quad single-pole/ single-throw (s pst) devices. the isl84521 has four normally closed (nc) s witches; the isl84522 has four normally open (no) switches; the isl84523 has two no and two nc switches and can be used as a dual spdt, or a dual 2:1 multiplexer. table 1 summarizes the performan ce of this family. for higher performance, pin compatible versions and 3mm x 3mm quad no-lead flatpack (qfn) package see the isl43140, isl43142 data sheet. features ? drop-in replacements for max4521 - max4523 ? four separately cont rolled spst switches ? pin compatible with dg411, dg412, dg413 ? on resistance (r on max.) . . . . . . . . . . . . . . . . . . . 100 ? ?r on matching between channels. . . . . . . . . . . . . . . . . . < 1 ?? ? low power consumption (p d ) . . . . . . . . . . . . . . . . . . . .<1 ? w ? low leakage current (max at 85 o c) . . . . . . . . . . . . 10na ? fast switching action -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns ? break before make timing ? minimum 2000v esd protection per method 3015.7 ? ttl, cmos compatible ? pb-free available applications ? battery powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? communications systems - military radios - rf tee switches ? test equipment - ultrasound - electrocardiograph ? heads-up displays ? audio and video switching ? general purpose circuits - +3v/+5v dacs and adcs - digital filters - operational amplifier gain switching networks - high frequency analog switching - high speed multiplexing related literature ? technical brief tb363 guidelines for handling and processing moisture sensit ive surface mount devices (smds) ? application note an557 recommended test procedures for analog switches table 1. features at a glance isl84521 isl84522 isl84523 number of switches 4 4 4 configuration all nc all no 2 nc/2 no ? 5v r on 65 ? 65 ? 65 ? ? 5v t on /t off 45ns/15ns 45ns/15ns 45ns/15ns 5v r on 125 ? 125 ? 125 ? 5v t on /t off 60ns/20ns 60ns/20ns 60ns/20ns 3v r on 260 ? 260 ? 260 ? 3v t on /t off 120ns/40ns 120ns/40ns 120ns/40ns packages 16 ld soic (n), 16 ld tssop data sheet august 10, 2015 caution: these devices are sensitive to electrostatic discharge ; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil ame ricas inc. copyright ? intersil americas llc. 2003, 2004, 2015. all rights reserved all other trademarks mentioned are the property of their respec tive owners.
2 pinouts (note 1) isl84521 (soic, tssop) top view isl84522 (soic, tssop) top view isl84523 (soic, tssop) top view note: 1. switches shown for logic 0 input. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in1 com1 nc1 v- gnd nc4 in4 com4 in2 nc2 v+ n.c. nc3 com3 in3 com2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in1 com1 no1 v- gnd no4 in4 com4 in2 no2 v+ n.c. no3 com3 in3 com2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in1 com1 no1 v- gnd no4 in4 com4 in2 nc2 v+ n.c. nc3 com3 in3 com2 truth table logic isl84521 isl84522 isl84523 sw 1, 2, 3, 4 sw 1, 2, 3, 4 sw 1, 4 sw 2, 3 0on offoffon 1 off on on off note: logic 0 ? 0.8v. logic 1 ?? 2.4v. pin descriptions pin function v+ positive power supply input v- negative power supply input. connect to gnd for single supply configurations. gnd ground connection in digital control input com analog switch common pin no analog switch normally open pin nc analog switch normally closed pin n.c. no internal connection ordering information part no. (note 2) temp. range ( o c) package (rohs compliant) pkg. dwg. # isl84521ibz* -40 to 85 16 ld soic (n) m16.15 isl84521ivz* -40 to 85 16 ld tssop m16.173 isl84522ibz* -40 to 85 16 ld soic (n) m16.15 isl84522ivz* -40 to 85 16 ld tssop m16.173 ISL84523IBZ* no longer available, recommended replacement: isl84524iuz-t) -40 to 85 16 ld soic (n) m16.15 isl84523ivz* no longer available, recommended replacement: isl84524iuz-t) -40 to 85 16 ld tssop m16.173 *add -t suffix to part number for tape and reel packaging. note: 2. intersil pb-free products employ special pb-free material set s; molding compounds/die attach materials and 100% matte tin plate termination finish, w hich is compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020b. isl84521, isl84522, isl84523
3 absolute maximum ratings thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15v v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15v v- to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3v all other pins (note 3) . . . . . . . . . . . . . ((v-) - 0.3v) to ((v+) + 0.3v) continuous current (an y terminal) . . . . . . . . . . . . . . . . . . . . . 10ma peak current, in, no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . 20ma esd rating (per mil-std-883 method 3015). . . . . . . . . . . . . > 2kv operating conditions temperature range isl8452xix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 4) ? ja ( o c/w) 16 ld soic package . . . . . . . . . . . . . . . . . . . . . . . . . . 115 16 ld tssop package . . . . . . . . . . . . . . . . . . . . . . 150 maximum junction temperat ure (plastic package). . . . . . . . 150 o c moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum storage temperature range . . . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. signals on nc, no, com, or in exceeding v+ or v- are clamped by internal diodes. limit forward diode current to maximum curr ent ratings. 4. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. electrical specifications +5v supply test conditions: v supply = ? 4.5v to ? 5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 5), unless otherwise specified parameter test conditions temp ( o c) (note 6) min typ (note 6) max units analog switch characteristics analog signal range, v analog full v- - v+ v on resistance, r on v s = ? 5v, i com = 1.0ma, v no or v nc = ? 3v (figure 5) 25 - 65 100 ? full - - 125 ? r on matching between channels, ? r on v s = ? 5v, i com = 1.0ma, v no or v nc = ? 3v 25 - 1 4 ? full - - 6 ? r on flatness, r flat(on) v s = ? 5v, i com = 1.0ma, v no or v nc = ? 3v (note 8) 25 - 7 12 ? full - - 15 ? no or nc off leakage current, i no(off) or i nc(off) v s = ? 5.5v, v com = ? 4.5v, v no or v nc = + 4.5v (note 7) 25 -1 0.01 1 na full -10 - 10 na com off leakage current, i com(off) v s = ? 5.5v, v com = ? 4.5v, v no or v nc = + 4.5v (note 7) 25 -1 0.01 1 na full -10 - 10 na com on leakage current, i com(on) v s = ? 5.5v, v com = v no or v nc = ? 4.5v (note 7) 25 -2 0.01 2 na full -20 - 20 na digital input characteristics input voltage high, v inh full - 1.6 2.4 v input voltage low, v inl full 0.8 1.6 - v input current, i inh , i inl v s = ? 5.5v, v in = 0v or v+ full -1 0.03 1 ? a dynamic characteristics turn-on time, t on v s = ? 4.5v, v no or v nc = ? 3v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 1) 25 - 45 80 ns full - - 100 ns turn-off time, t off v s = ? 4.5v, v no or v nc = ? 3v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 1) 25 - 15 30 ns full - - 40 ns break-before-make time delay (isl84523), t d v s = ? 5.5v, v no or v nc = ? 3v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 3) 25 5 20 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ? (figure 2) 25 - 1 5 pc no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v (figure 7) 25 - 2 - pf com off capacitance, c com(off) f = 1mhz, v no or v nc = v com = 0v (figure 7) 25 - 2 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v (figure 7) 25 - 5 - pf isl84521, isl84522, isl84523
4 off isolation r l = 50 ? , c l = 15pf, f = 100khz, v no or v nc = 1v rms , (see figures 4 and 6) 25 - >90 - db crosstalk, (note 9) 25 - <-90 - db power supply characteristics power supply range full ? 2- ? 6v positive supply current, i+ v s = ? 5.5v, v in = 0v or v+, switch on or off 25 -1 0.05 1 ? a full -1 - 1 ? a negative supply current, i- 25 -1 0.05 1 ? a full -1 - 1 ? a notes: 5. v in = input voltage to perform proper function. 6. the algebraic convention, wher eby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25 o c. 8. flatness is defined as the del ta between the maximum and mini mum r on values over the specified voltage range. 9. between any two switches. electrical specifications 5v supply test conditions: v+ = +4.5v to +5.5v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 5), unless otherwise specified parameter test conditions temp ( o c) min (note 6) typ max (note 6 )units analog switch characteristics analog signal range, v analog full 0 - v+ v on resistance, r on v+ = 4.5v, i com = 1.0ma, v no or v nc = 3.5v (figure 5) 25 - 125 200 ? full - - 250 ? r on matching between channels, ? r on v+ = 5v, i com = 1.0ma, v no or v nc = 3.5v 25 - 2 8 ? full - - 10 ? no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 1v, 4.5v, v no or v nc = 4.5v, 1v (note 7) 25 -1 0.01 1 na full -10 - 10 na com off leakage current, i com(off) v+ = 5.5v, v com = 1v, 4.5v, v no or v nc = 4.5v, 1v (note 7) 25 -1 0.01 1 na full -10 - 10 na com on leakage current, i com(on) v+ = 5.5v, v com = 1v, 4.5v (note 7) 25 -2 - 2 na full -20 - 20 na digital input characteristics input voltage high, v inh full - 1.6 2.4 v input voltage low, v inl full 0.8 1.6 - v input current, i inh , i inl v+ = 5.5v, v in = 0v or v+ full -1 0.03 1 ? a dynamic characteristics turn-on time, t on v+ = 4.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 1) 25 - 60 100 ns full - - 150 ns turn-off time, t off v+ = 4.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 1) 25 - 20 50 ns full - - 75 ns break-before-make time delay (isl84523), t d v+ = 5.5v, v no or v nc = 3v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 3) 25 10 30 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ??? figure 2) 25 - 1 5 pc electrical specifications +5v supply test conditions: v supply = ? 4.5v to ? 5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 5), unless otherwise specified (continued) parameter test conditions temp ( o c) (note 6) min typ (note 6) max units isl84521, isl84522, isl84523
5 power supply characteristics positive supply current, i+ v+ = 5.5v, v in = 0v or v+, switch on or off 25 -1 0.05 1 ? a full -1 - 1 ? a negative supply current, i- 25 -1 0.05 1 ? a full -1 - 1 ? a electrical specifications 3v supply test conditions: v+ = +2.7v to +3.6v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 5), unless otherwise specified parameter test conditions temp ( o c) min (note 6) typ max (note 6 )units analog switch characteristics analog signal range, v analog full 0 - v+ v on resistance, r on v+ = 2.7v, i com = 0.1ma, v no or v nc = 1v 25 - 260 500 ? full - - 600 ? digital input characteristics input voltage high, v inh full - 1.6 2.4 v input voltage low, v inl full 0.8 1.6 - v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -1 0.03 1 ? a dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 300 ? , c l = 35pf, v in = 0 to v+ (figure 1) 25 - 120 250 ns full - - 300 ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 300 ? , c l = 35pf, v in = 0 to v+ (figure 1) 25 - 40 80 ns full - - 100 ns break-before-make time delay (isl84523), t d v+ = 3.6v, v no or v nc = 1.5v, r l = 300 ? , c l = 35pf, v in = 0 to 3v (figure 3) 25 15 50 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 ??? figure 2) 25 - 0.5 5 pc power supply characteristics positive supply current, i+ v+ = 3.6v, v in = 0v or v+, switch on or off 25 -1 0.05 1 ? a full -1 - 1 ? a negative supply current, i- 25 -1 0.05 1 ? a full -1 - 1 ? a test circuits and waveforms logic input waveform is inverted for switches that have the opp osite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times electrical specifications 5v supply test conditions: v+ = +4.5v to +5.5v, v- = gnd = 0v, v inh = 2.4v, v inl = 0.8v (note 5), unless otherwise specified (continued) parameter test conditions temp ( o c) min (note 6) typ max (note 6 )units 50% t r < 20ns t f < 20ns t off 90% 3v 0v v nx 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on ?? + ------------------------------ = ? 35pf gnd v+ c v- c v nx c isl84521, isl84522, isl84523
6 logic input waveform is inverted for switches that have the opp osite logic sense. figure 2a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 2b. test circuit figure 2. charge injection figure 3a. measurement points c l includes fixture and stray capacitance. reconfigure accordingly to test sw3 and sw4. figure 3b. test circuit figure 3. break-before-make time (isl84523 only) repeat test for all switches. figure 4. off isolation test circuit repeat test for all switches. figure 5. r on test circuit test circuits and waveforms (continued) v out ? v out on off on q = ? v out x c l switch output logic input 3v 0v c l v out r g v g gnd com no or nc v+ c logic input in c v- 90% 3v 0v t d 0v logic input switch output switch output 90% t d 0v v out1 v out2 90% 90% logic input in1 com1 r l1 c l1 v out1 300 ? 35pf com2 r l2 c l2 v out2 300 ? 35pf no1 nc2 gnd in2 v nx v+ c c v- c analyzer r l signal generator v+ c 0v or 2.4v no or nc com in gnd c v- v+ c 0.8v or 2.4v no or nc com in gnd v nx v 1 r on = v 1 /1ma 1ma c v- isl84521, isl84522, isl84523
7 detailed description the isl84521, isl84522, isl 84523 quad analog switches offer precise switching capability from a bipolar ? 2v to ? 6v or a single 2v to 12v supply with low on-resistance (65 ? ) and high speed switching (t on = 45ns, t off = 15ns). the devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2v), low power consumption (1 ? w) and low leakage currents (1na max). high frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. supply sequencing and overvoltage protection as with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanent ly damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to v- (figure 8). to prevent forwa rd biasing these diodes, v+ and v- must be applied before any input signals, and input signal voltages must remai n between v+ and v-. if these conditions cannot be guarante ed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k ? resistor in series with the inpu t (figure 8). the resistor limi ts the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. adding a series resistor to t he switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for a ll pins (figure 8). these additional diodes limit the analog signal from 1v below v+ to 1v above v-. the low leakag e current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. power-supply considerations the isl8452x construction is typical of most cmos analog switches, in that they have th ree supply pins: v+, v-, and gnd. v+ and v- drive the inte rnal cmos switches and set their analog voltage limits, s o there are no connections between the analog signal pat h and gnd. unlike switches with a 13v maximum supply vo ltage, the isl8452x 15v maximum supply voltage provid es plenty of room for the 10% tolerance of 12v supplies ( ? 6v or 12v single supply), as well as room for over shoot and noise spikes. this family of switches perfo rms equally well when operated with bipolar or single voltage s upplies, and bipolar supplies need not be symmetrical. the minimum recommended supply voltage is 2v or ? 2v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the electrical specification tables and typical performance curves for details. figure 6. crosstalk test circuit figure 7. capacitance test circuit test circuits and waveforms (continued) 0v or 2.4v analyzer v+ c no1 or nc1 signal generator r l gnd in2 com1 in2 50 ? 0v or 2.4v no com2 no2 or nc2 c v- connection v+ gnd no or nc com in impedance analyzer 0v or 2.4v v- figure 8. overvoltage protection v- v com v no or nc optional protection v+ in x diode optional protection diode optional protection resistor isl84521, isl84522, isl84523
8 v+ and gnd power the internal logic (thus setting the digital switching point) and level shifte rs. the level shifters convert the logic levels to switched v+ a nd v- signals to drive the analog switch gate terminals, so switch parameters - especially r on - are strong functions of both supplies. logic-level thresholds v+ and gnd power the internal logic stages, so v- has no affect on logic thresholds . this switch family is ttl compatible (0.8v and 2.4v) ov er a v+ supply range of 2.5v to 10v. at 12v the v ih level is about 2.7v, so for best results use a logic family the provides a v oh greater than 3v. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. drivin g the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 ?? systems, signal response is reasonably flat even past 300mhz (figure 15), with a s mall signal -3db bandwidth in excess of 400mhz, and a larg e signal bandwidth exceeding 300mhz. an off switch acts like a ca pacitor and passes higher frequencies with less attenua tion, resulting in signal feedthrough from a switchs input to its output. off isolation is the resistance to this f eedthrough, while crosstalk indicates the amount of feedt hrough from one switch to another. figure 16 details t he high off isolation and crosstalk rejection provided by this family. at 10mhz, off isolation is about 50db in 50 ?? systems, decreasing approximately 20db per deca de as frequency increases. higher load impedances dec rease off isolation and crosstalk rejection due to the voltage div ider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and v-. one of these diodes conducts if any analog signal exceeds v+ or v-. virtually all the analog leakage current comes from the esd diodes to v+ or v-. although the esd diodes on a given signal pin are identical and t herefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or v- and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and v- pins constitutes the analog-signal- path leakage current . all analog leakag e current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage currents of the same or opposite polarity. there is no connecti on between the analog signal paths and gnd. typical performance curves t a = 25 o c, unless otherwise specified figure 9. on resistance vs supply voltage figure 10. on resistance vs switch voltage 40 50 60 70 80 90 r on ( ? ) v+ (v) v com = (v+) - 1v i com = 1ma 4 6 8 10 12 0 50 100 150 200 250 357911 v- = -5v 25 o c -40 o c 85 o c -40 o c 85 o c 25 o c v- = 0v 50 100 150 200 250 300 r on ( ? ) v com (v) 024 50 80 110 140 135 v+ = 2.7v v+ = 5v 25 o c -40 o c 85 o c i com = 1ma v- = 0v v- = 0v 75 125 175 225 v+ = 3.3v 25 o c -40 o c 85 o c v- = 0v 25 o c 85 o c -40 o c isl84521, isl84522, isl84523
9 figure 11. on resistance vs switch voltage figure 12. charge inject ion vs switch voltage figure 13. turn - on time vs supply voltage figure 14. turn - off time vs supply voltage typical performance curves t a = 25 o c, unless otherwise specified (continued) r on ( ? ) v com (v) -4-2024 30 50 70 90 -5 -3 -1 1 3 5 v s = ?? 5v 40 60 80 100 120 v s = ?? 3v 60 100 140 180 i com = 1ma v s = ?? 2v 25 o c 85 o c 25 o c -40 o c 85 o c 25 o c -40 o c 85 o c -40 o c q (pc) v com (v) -5 0 5 -5 0 5 -2.5 2.5 -7.5 2.5 2.5 v s = ?? 5v v+ = 5v v+ = 3.3v t on (ns) v+ (v) 24681012 0 50 100 150 200 250 300 357911 -40 o c 85 o c 25 o c v- = 0v 0 50 100 150 200 250 v- = -5v v com = (v+) - 1v -40 o c 85 o c -40 o c 25 o c 25 o c t off (ns) v+ (v) 24681012 10 20 30 40 50 357911 -40 o c 85 o c 25 o c 0 50 100 25 75 125 v com = (v+) - 1v v- = 0v v- = -5v -40 o c 85 o c -40 o c 25 o c 25 o c isl84521, isl84522, isl84523
10 die characteristics substrate potentia l (powered up): v- transistor count: isl84521: 188 isl84522: 188 isl84523: 188 process: si gate cmos figure 15. frequency response figure 16. crosstalk and off isolation typical performance curves t a = 25 o c, unless otherwise specified (continued) frequency (mhz) 3 0 -3 normalized gain (db) 0 45 90 135 180 phase (degrees) 1 10 100 600 v in = 5v p-p v in = 5v p-p v in = 0.2v p-p v in = 0.2v p-p gain phase v s = ? 5v r l = 50 ? ??? ??? ???? ?? ? 2v to ? 5v v+ = 3v to 12v or r l = 50 ? isl84521, isl84522, isl84523
11 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change august 10, 2015 fn6031.4 updated ordering information table on pa ge 2. added revision history and about intersil sections. updated package outline drawing (pod) m16.173 with the latest v ersion. changes from rev. 1 to rev 2 are as follows: -convert to new pod format by mov ing dimensions from table onto drawing and adding land pattern. no dimension changes. isl84521, isl84522, isl84523
12 isl84521, isl84522, isl84523 small outline plast ic packages (soic) notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 ? 0 8 0 8 - rev. 1 6/05
13 isl84521, isl84522, isl84523 package outline drawing m16.173 16 lead thin shrink small outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burr s. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include inter lead flash or protrusion. inter lead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrus ion shall be 0.08mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m

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